Optimizing Dynamic Hardware Reconfigurations

Teich, Jürgen and Fekete, Sandor P. and Schepers, Jörg (1998) Optimizing Dynamic Hardware Reconfigurations.
Technical Report , 12 p.


With the advent of recent generations of Field Programmable Gate Arrays, it has become possible to use computing resources more efficiently by dynamically reconfiguring hardware (during run-time). This is achieved by reassigning computation modules or tasks to unused cells. For a given problem consisting of a set of tasks, possibly with partial order constraints, we consider problems such as finding the minimal area chip to accomplish the tasks within a given time limit. These problems turn out to be multi-dimensional packing problems. With the new notion of packing classes, we show how the search space may be significantly reduced, such that these problems can be solved exactly in an affordable amount of time for problems of technical interest using special branch-and-bound techniques. We validate the usefulness of our method by providing computational results.

Download: [img] Postscript
Download (1MB) | Preview
Editorial actions: View Item View Item (Login required)
Deposit Information:
ZAIK Number: zpr98-336
Depositing User: Archive Admin
Date Deposited: 02 Apr 2001 00:00
Last Modified: 16 Jan 2012 15:35
URI: http://e-archive.informatik.uni-koeln.de/id/eprint/336